%FILENAME%
vtr-8.0.0-4-x86_64.pkg.tar.zst

%NAME%
vtr

%BASE%
vtr

%VERSION%
8.0.0-4

%DESC%
Verilog to Routing -- Open Source CAD Flow for FPGA Research

%CSIZE%
6525293

%ISIZE%
20454327

%MD5SUM%
b1c9e264e765bb9e496a87906ac243a5

%SHA256SUM%
9faba96d6ecb95d5e5af5e542690f0075d0bc57d1f046b13562de7f167e4792e

%PGPSIG%
iQJIBAABCAAyFiEE6HyevZCe8oInuRJWULwdtYO3lwYFAmNhOrwUHGFzbWVyb25AdWJsaW51eC5jb20ACgkQULwdtYO3lwYtsRAAlSSrcKiv6idBt4uty4kaQ8dS1U2AYwEUuwAk9J8/y1ISZPZ/7eBOx3oFxOs3Q/9uyj74jABVbvTZmNvwYUsIQLEjrxTGgwedvZjpE8cPfHmHjZQ6vBj3XDTNf0nnY+mTphtvck7tCSEYnb3SWAUh4zUNQh6n+HbG76RY5tYnr1zRpUv3aG/MXUguGE4sm4skLs0GfKoZx5BKHeEncEhm3+bRoodN3ORkvIiAwKt2bEB2ue6QjA+aLEYXn2b/YAO3D83DDWcn3/ucR0rWsd31RYi/cNwjEu2+IHyVRu6KpTSxr+D3BNZvS2FglRYHvKfHGvjHTVqZh4lzJI630MR07PzJHoW7lay1Us9NzRc+FeP2XWb1W3+Fdz0P+KE3PeOAhEWghcSfLOU9ZIezfxoicRGo7avURibueSs+HahFWMUg1wsDQ4sCh8yVcJw35ALbcveYv0eKz4iibWV2Y0NfCxOiu2N2urww19E2goM9f1YkN4WqDwzDMpNxCL2250DI/gkkN1dCpdxL/oxCYKNq4Wc/cE12R6MasXbzX+C+MS7cLKDXU3tqTU0tyMOxp87BFfoZq0V+3sUmWNx9O3Pr+iCx4STyy2PPdJKayJe27D/wYD8Sy0obm6AdPjJI8onEkNXw3ymI63zKLBbFhEQNDQh+PBTDYzmYkVZhR2tT9Y8=

%URL%
https://verilogtorouting.org

%LICENSE%
MIT

%ARCH%
x86_64

%BUILDDATE%
1637948324

%PACKAGER%
Antonio Rojas <arojas@archlinux.org>

%DEPENDS%
ctags
tbb

%MAKEDEPENDS%
cmake

